1. FIELD OF THE INVENTION
This invention relates to monolithic integrated semiconductor devices, and in particular to a vertical bipolar power transistor with buried base and interdigitated geometry.
2. DESCRIPTION OF THE PRIOR ART
A bipolar transistor of this type is described in Italian Patent Application MI91A/03159 filed by the Applicant on 26.11.91. This is manufactured using a process known as VIPower (a trademark of SGS-THOMSON MICROELECTRONICS s.r.l.) and described in European Patent Application EP-322040 by SGS-THOMSON MICROELECTRONICS s.r.l., which is specially conceived to provide integrated structures including power devices and signal processing circuitry for controlling the power devices. Shown in FIG. 1 of the accompanying drawings is a sectional view of a portion of an integrated structure described in the above Italian Patent Application. The integrated structure 50 is a chip of semiconductor material of the N type.
The structure manufacturing process can be summarized as follows. Formed by epitaxial growth on a substrate 10 of monocrystalline silicon, as heavily doped with impurities of the N type, is a first layer 11 having the same type of N conductivity but a lower concentration of impurities. Note that the concentrations of N-type and P-type impurities are customarily denoted by adding the sign "+" or the sign "-" to the characters N and P; the characters N and P with no "+" or "-" sign added denote concentrations of medium value. Formed by implantation on the surface of the epitaxial layer 11 are P-type regions having a comparatively low impurity concentration, followed by N-type regions having high impurity concentrations and being implanted over said P-type regions. A second layer 12 of the N type having a higher concentration of impurities than the first layer 11 is then formed over the layer 11 by epitaxial growth. During this step, which is carried out at a high temperature, the implanted regions of the P type and the N type spread through the two epitaxial layers to produce buried regions, as respectively indicated at 13 and 14 in the drawings, which form together a junction and are to provide the base region and emitter region, respectively, of the bipolar power transistor.
Formed then in the second epitaxial layer 12, using conventional masking and diffusion techniques, are regions of the P type which have high concentrations of impurities, indicated at 15, through-penetrating the second epitaxial layer 12 to join the region 13 and constitute the deep contact base regions of the transistor.
Using similar techniques, regions 17 of the N type are subsequently formed which have high impurity concentrations and extend as far as the respective buried emitter regions to provide deep emitter contacts and regions 16 of the N type, also at high concentrations, which constitute, together with their respective regions 17, interconnection regions between the emitter regions and the front surface of the chip. Such interconnection regions 16 and 17 have resistivities and sizes adequate to provide emitter ballast resistors.
Subsequently, on the front surface of the chip which is coated with a layer of silicon dioxide indicated at 9, metallic strips 18 and 19 are formed using conventional deposition, masking, and etching techniques, which strips are in contact with respective surface areas of the regions 15 and 16 to form the transistor base and emitter electrodes, respectively, and are led to base B and emitter E termination areas of the transistor, respectively. On the chip bottom, i.e. on the exposed surface of the substrate 10, there is formed a metallic layer 28 which constitutes the collector terminal C of the transistor.
The above-described structure shows in plan view a so-called interdigitated construction, i.e. one formed by an emitter region which extends into a comb-like pattern--or pattern having elongate portions being the regions 14 in FIG. 1--within the base region 13. An interconnection region, consisting of a deep emitter contact portion 17 and an expanded surface portion 16, extends across each of the elongate portions 14, and deep contact base regions 15 extend between adjacent elongate portions 14. The single strips which form the emitter and base electrodes are interleaved like crossed fingers of two hands, whence the expression "interdigitated geometry".
The prior art transistor just described has an emitter with a very high perimeter-to-area ratio, and when the emitter resistances are properly dimensioned, an even current distribution to the various "fingers" of the emitter. Briefly stated, it can operate on large currents while having small bulk. However, it has been found that when operated at a high voltage and a large current, the prior transistor is beset with limitations that should not appear according to theory.
Specifically, the safe operating area (SOA) of the transistor is found smaller than estimated, and the current gain during operation at high collector current levels is less than could be anticipated of a transistor provided with the above-described structure.